Simplified drain current model for pinch‐off double gate junctionless transistor
Author:
Affiliation:
1. Indian Institute of Information Technology, Design and ManufacturingJabalpur482 005Madhya PradeshIndia
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2013.3342
Reference6 articles.
1. Pinch‐off mechanism in double‐lateral‐gate junctionless transistors fabricated by scanning probe microscope based lithography;Larki F.;Beilstein J. Nanotechnol.,2012
2. Surface-Potential-Based Drain Current Model for Long-Channel Junctionless Double-Gate MOSFETs
3. Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors
4. Modeling of a nonpinchoff depletion mode MOSFET;Biehl B.L.;IEEE J. Solid‐State Circuits,1980
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