Model for clipping‐induced timing error of bandwidth‐limited comparators
Author:
Affiliation:
1. Chair of Electronics and CircuitsSaarland UniversityGermany
2. STmicroelectronicsCrollesFrance
3. Ampere LabINSA LyonFrance
4. MICRAM Microelectronics GmbHBochumGermany
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2013.0012
Reference4 articles.
1. Sinusoidal clock sampling for multigigahertz ADCs;Bai R.;IEEE Trans. Circuits Syst.,2011
2. A low propagation delay dispersion comparator for a level‐crossing AD converter;Kozmin K.;Analog Integr. Circuits Signal Process.,2010
3. Over‐30‐GHz limiting amplifier IC's with small phase deviation for optical communication systems;Nakamura M.;IEEE J. Solid‐State Circuits,1996
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