Hierarchical architecture for area-efficient integrated N-port memories with latency-free multi-gigabit per second access bandwidth
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el_19990974?crawler=true&mimetype=application/pdf
Reference6 articles.
1. Buffered banks in multiprocessor systems
2. Application of port-access-rejection probability theory for integrated N-port memory architecture optimisation
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3. Distributed against centralised crossbar function for realising bank-based multiport memories;Electronics Letters;2004
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