Threshold voltage tuning and suppression of edge effects in narrow channel MOSFETs using surrounding buried side-gate
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el_20057152?crawler=true&mimetype=application/pdf
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1. Power-constrained CMOS scaling limits
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