A 10‐GHz bandwidth 45.5‐dB SNDR buffer with local feedback in 45‐nm CMOS
Author:
Affiliation:
1. School of Information Science and Engineering Southeast University Nanjing Jiangsu China
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/ell2.12710
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4. A High‐linearity Input‐Buffer with high output common‐mode stability for 10bit 3.2GSs ADC
5. Chen Y. Hu H. Ye F. Ren J.:A wide‐band input buffer for 3GS/s 12bit time‐interleaved ADC. In:2016 13th IEEE International Conference on Solid‐State and Integrated Circuit Technology (ICSICT) pp.1467–1469(2016).https://doi.org/10.1109/ICSICT.2016.7998771
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