Controlled behaviour of STF in CT modulators
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el_20051456?crawler=true&mimetype=application/pdf
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5. Oppenheim, A.V., Schafer, R.W., and Buck, J.R.: ‘Discrete-time signal processing’, 2nd(Prentice-Hall International 1999)
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2. A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS;IEEE Journal of Solid-State Circuits;2021-01
3. Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-04
4. Analysis and Modeling of Chopping Phase Non-Overlap in Continuous-Time $\Delta\Sigma$ Modulators;IEEE Transactions on Circuits and Systems I: Regular Papers;2018-10
5. Design-to-testing: a low-power, 1.25 GHz, single-bit single-loop continuous-time $$\Delta \Sigma$$ Δ Σ modulator with 15 MHz bandwidth and 60 dB dynamic range;Analog Integrated Circuits and Signal Processing;2016-09-16
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