Completely iterative, pipelined multiplier array suitable for VLSI-Reference-Cited by-同舟云学术

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Completely iterative, pipelined multiplier array suitable for VLSI

Published:1982 Issue:2 Volume:129 Page:40
ISSN:0143-7089
Container-title:IEE Proceedings G (Electronic Circuits and Systems)
language:en
Short-container-title:IEE Proc. G Electron. Circuits Syst. UK

Author:

McCanny J.V.,McWhirter J.G.

Publisher

Institution of Engineering and Technology (IET)

Subject

General Engineering

Link

https://digital-library.theiet.org/content/journals/10.1049/ip-g-1.1982.0008?crawler=true&mimetype=application/pdf

Reference22 articles.

1. Mead, C.A., and Conway, L.A.: Introduction to VLSI systems, (Addison-Wesley 1980)

2. ‘A guide to LSI implementation’, XEROX PARC Technical Report, 1979 2nd edn

3. Kung, H.T., and Leiserson, C.R.: ‘Systolic arrays (for VLSI)’, Buff, I.S., Stewart, G.W., Sparse matrices proc, (Society for Industrial and Applied Mathematics 1978), p. 256–282

Cited by 32 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Multiplexer-based array multipliers;IEEE Transactions on Computers;1999

2. Cell delay fault testing for iterative logic arrays;Journal of Electronic Testing;1996-12

3. Radix multiplication algorithms;International Journal of Electronics;1995-09

4. VLSI architectures for vector quantization;Journal of VLSI signal processing systems for signal, image and video technology;1995-06

5. C-testable design techniques for iterative logic arrays;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;1995-03

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