Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Cited by
16 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Check-and-Balance Scheme in Multiphase Delay-Locked Loop;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-07
2. Optimization of DCO Using Latch-Based Varactor Cells for a Cell-Based PLL;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06
3. Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022
4. Tiny Phase-Error Monitor for Fault and Soft-Error Tolerant DLL To Support Graceful Degradation and Module-Level Testing;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021
5. Process Resilient Fault Tolerant Delay Locked Loop using TMR with Dynamic Timing Correction;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021