Allocating resources based on a model of coarse‐grained reconfigurable architecture

Author:

Zhang Huizhen1,Pan Yubiao1,Zhang Yiwen1,Wang Cheng1

Affiliation:

1. College of Computer Science and Technology, Huaqiao UniversityNo.668 Jimei AvenueXiamenPeople's Republic of China

Funder

National Natural Science Foundation of China

Publisher

Institution of Engineering and Technology (IET)

Subject

General Engineering,Energy Engineering and Power Technology,Software

Reference19 articles.

1. JainM.K. BalakrishnanM. KumarA.: ‘ASIP design methodologies: survey and issues’.Proc. Int. Conf. VLSI Design Los Alamitos CA 2001 pp.76–81

2. The instruction‐set extension problem: a survey;Galuzzi C.;ACM Trans. Reconfigurable Technol. Syst.,2011

3. BaratF. LauwereinsR.: ‘Reconfigurable instruction set processors: a survey’.Proc. Int. Workshop on Rapid System Prototyping Los Alamitos CA 2000 pp.168–173

4. AlfkeP.: ‘Xilinx Virtex‐6 and Spartan‐6 FPGA families’.Proc. Hot Chips 21 Symp. Stanford CA 2009 pp.1–20

5. LewisD. AhmedE. BaecklerG.et al.: ‘The Stratix II logic and routing architecture’.Proc. Int. Symp. on Field‐Programmable Gate Arrays New York 2005 pp.14–20

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