Low voltage CMOS four-quadrant multiplier
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el_19941427?crawler=true&mimetype=application/pdf
Reference10 articles.
1. CMOS four-quadrant multiplier using bias offset crosscoupled pairs
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1. 130 nm Low Power CMOS Analog Multiplier;Journal of Physics: Conference Series;2018-07
2. Low voltage four‐quadrant analog multiplier using dynamic threshold MOS transistors;Microelectronics International;2009-01-23
3. Design of highly linear multipliers using floating gate transistors and/or source degeneration resistor;2008 IEEE International Symposium on Circuits and Systems;2008-05
4. A low-power CMOS analog multiplier;IEEE Transactions on Circuits and Systems II: Express Briefs;2006-02
5. A low-power low-noise CMOS analogue multiplier;IEE Proceedings - Circuits, Devices and Systems;2006
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