Counter‐example generation procedure for path‐based equivalence checkers
Author:
Affiliation:
1. Department of Computer Science and Engineering Indian Institute of Technology Guwahati 781 039 India
2. Intel Labs Bangalore India
Publisher
Institution of Engineering and Technology (IET)
Subject
Computer Graphics and Computer-Aided Design
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-sen.2018.5203
Reference28 articles.
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3. Kim Y. Kopuri S. Mansouri N.: ‘Automated formal verification of scheduling process using finite state machines with datapath (FSMD)’.Int. Symp. Quality Electronic Design San Jose CA USA March2004 pp.110–115
4. An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis
5. Translation validation of high-level synthesis;Kundu S.;IEEE Trans CAD ICS,2010
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1. VP_TT: A value propagation based equivalence checker for testability transformations;IET Software;2021-01-26
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