Low‐power charge‐steering phase interpolator
Author:
Affiliation:
1. EECE DepartmentAin Shams UniversityCairoEgypt
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2015.3968
Reference6 articles.
1. A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology
2. A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication
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