Digital encoding calibrated unit used in 8 bit 1 GS/s folding and interpolating ADC
Author:
Affiliation:
1. Institute of RF‐ and OE‐ICs, School of Information Science and Engineering, Southeast UniversityNanjing210096People's Republic of China
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2015.3934
Reference5 articles.
1. A 6‐bit 1.3G sample/s A/D converter in 0.35 μm CMOS;Choi M.;IEEE J. Solid‐State Circuits.,2001
2. A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture
3. A 5b 10GSample/s A/D converter for 10 Gb/s optical receivers;Lee J.;IEEE J. Solid‐State Circuit,2004
4. Improved sense‐amplifier‐based flip‐flop:design and measurements;Nikolic B.;IEEE Trans. Circuits Syst.,2010
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