Double‐sampled ΔΣ modulator with 1.5‐bit FIR feedback DAC for reduced noise folding and increased power efficiency-Reference-Cited by-同舟云学术

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Double‐sampled ΔΣ modulator with 1.5‐bit FIR feedback DAC for reduced noise folding and increased power efficiency

Published:2016-04 Issue:8 Volume:52 Page:598-600
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. lett.

Author:

Choi Moo‐Yeol¹²,Roh Hyung‐Dong²,Lee Yong‐Hee²,Park Ho‐Jin²,Kong Bai‐Sun¹

Affiliation:

1. Sungkyunkwan UniversitySuwonGyeonggi‐do440‐746Republic of Korea

2. Samsung ElectronicsYonginGyeonggi‐do446‐711Republic of Korea

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2015.3848

Reference4 articles.

1. A 0.5-V 35-$ \mu $W 85-dB DR Double-Sampled $\Delta\Sigma$ Modulator for Audio Applications

2. A high‐performance multibit ΔΣ CMOS ADC;Geerts Y.;IEEE J. Solid‐State Circuits,2000

3. An approach to tackle quantization noise folding in double‐sampling ΣΔ modulation A/D converters;Rombouts P.;IEEE Trans. Circuits Syst. II Analog Digit. Signal Process.,2003

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