Implementation of low-power FFT processor cores using a novel order-based processing scheme-Reference-Cited by-同舟云学术

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Implementation of low-power FFT processor cores using a novel order-based processing scheme

Published:2003 Issue:3 Volume:150 Page:149
ISSN:1350-2409
Container-title:IEE Proceedings - Circuits, Devices and Systems
language:en
Short-container-title:IEE Proc., Circuits Devices Syst.

Author:

Hasan M.,Arslan T.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://digital-library.theiet.org/content/journals/10.1049/ip-cds_20030347?crawler=true&mimetype=application/pdf

Reference13 articles.

1. Circuit techniques for CMOS low-power high-performance multipliers

2. Rabiner, L.R., and Gold, B.: ‘Theory and application of digital signal processing’, (Prentice-Hall, Englewood Cliffs, NJ 1975)

3. A low-power, high-performance, 1024-point FFT processor

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Analog implementation of radix-2, 16-FFT processor for OFDM receivers: non-linearity behaviours and system performance analysis;International Journal of Electronics;2015-04-16

2. Analog DFT Processors for OFDM Receivers: Circuit Mismatch and System Performance Analysis;IEEE Transactions on Circuits and Systems I: Regular Papers;2009-09

3. Scalable FFT Processors and Pipelined Butterfly Units;Journal of VLSI signal processing systems for signal, image and video technology;2006-06

4. A Low Power Architecture for a MC-CDMA Receiver;IETE Journal of Research;2005-11

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