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Efficient parallel adder based design for one-dimensional discrete cosine transform

  • Published:2000 Issue:5 Volume:147 Page:276
  • ISSN:1350-2409
  • Container-title:IEE Proceedings - Circuits, Devices and Systems
  • language:en
  • Short-container-title:IEE Proc., Circuits Devices Syst.

Author:

Guo J.-I.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Reference20 articles.

1. Rao, K.R., and Hwang, J.J.: ‘Techniques and standards for image, video and audio coding’, (Prentice Hall Inc. New Jersey 1996)

2. VLSI architectures for video compression-a survey

3. Fast algorithm for computing discrete cosine transform

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1. New fast and area-efficient pipeline 3-D DCT architectures;Digital Signal Processing;2019-01

2. Novel Structures for Cyclic Convolution Using Improved First-Order Moment Algorithm;IEEE Transactions on Circuits and Systems I: Regular Papers;2014-08

3. A memory-efficient realization of cyclic convolution and its application to discrete cosine transform;IEEE Transactions on Circuits and Systems for Video Technology;2005-03

4. Design and realisation of a new hardware efficient IP core for the 1-D discrete Fourier transform;IEE Proceedings - Circuits, Devices and Systems;2005

5. Efficient systolic array mapping of FIR filters used in PAM-QAM modulators;The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology;2003
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