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Reduced complexity 1-bit high-order digital delta-sigma modulator for low-voltage fractional-N frequency synthesis applications

  • Published:2005 Issue:5 Volume:152 Page:471
  • ISSN:1350-2409
  • Container-title:IEE Proceedings - Circuits, Devices and Systems
  • language:en
  • Short-container-title:IEE Proc., Circuits Devices Syst.

Author:

Bornoosh B.,Afzali-Kusha A.,Dehghani R.,Mehrara M.,Atarodi S.M.,Nourani M.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Comparative Study of Delta-Sigma Modulators for the Fractional-N PLL in WBAN;Lecture Notes in Electrical Engineering;2013-06-15

2. A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 $\mu$m CMOS;IEEE Journal of Solid-State Circuits;2012-12

3. Hardware Reduction in Digital Delta-Sigma Modulators Via Bus-Splitting and Error Masking—Part I: Constant Input;IEEE Transactions on Circuits and Systems I: Regular Papers;2011-09

4. Reduced Complexity MASH Delta–Sigma Modulator;IEEE Transactions on Circuits and Systems II: Express Briefs;2007-08
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