Design of frequency‐interleaved ADC with mismatch compensation
Author:
Affiliation:
1. School of Electrical and Electronic EngineeringNanyang Technological University50 Nanyang AvenueSingapore
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2014.0577
Reference5 articles.
1. A four‐channel time‐interleaved ADC with digital calibration of interchannel timing and memory errors;Chi Ho L.;IEEE J. Solid‐State Circuits,2010
2. Design of hybrid filter banks for analog/digital conversion
3. Design and multiplierless realization of digital synthesis filters for hybrid‐filter‐bank A/D converters;Zhao S.H.;IEEE Trans. Circuits Syst. I, Reg. Pprs.,2009
4. Comprehensive digital correction of mismatch errors for a 400‐msamples/s 80‐dB SFDR time‐interleaved analog‐to‐digital converter;Munkyo S.;IEEE Trans. Microw. Theory Tech.,2005
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