DECO: DIMM controller efficient for ECC operations
Author:
Affiliation:
1. Department of Electronics and Electrical EngineeringDankook UniversityJukjeon‐Dong, Suji‐GuYongin‐City448Kyunnggi‐DoRepublic of Korea
Funder
Dankook University
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2014.1135
Reference6 articles.
1. JEDEC specifications: ‘DDR 1 2 and 3 SDRAM Standard’. Available athttp://www.jedec.org accessed April 2014
2. An SDRAM‐aware router for networks‐on‐chip;Jang W.;IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.,2010
3. Sonics MemMax specification: ‘MemMax DRAM system’. Available athttp://sonicsinc.com accessed April 2014
4. Rate-constrained coder control and comparison of video coding standards
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2. Error-Correcting Code Aware Memory Subsystem;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2014-11
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