A Lightweight, Hardware-Based Support for Isolation in Mixed-Criticality Network-on-Chip Architectures-Reference-Cited by-同舟云学术

A Lightweight, Hardware-Based Support for Isolation in Mixed-Criticality Network-on-Chip Architectures

Published:2019 Issue:4 Volume:4 Page:561-573
ISSN:2415-6698
Container-title:Advances in Science, Technology and Engineering Systems Journal
language:
Short-container-title:Adv. sci. technol. eng. syst. j.

Author:

Valente Giacomo,Giammatteo Paolo,Muttillo Vittoriano,Pomante Luigi,Mascio Tania Di

Publisher

ASTES Journal

Subject

Management of Technology and Innovation,Physics and Astronomy (miscellaneous),Engineering (miscellaneous)

Link

https://www.astesj.com/publications/ASTESJ_040467.pdf

Reference21 articles.

1. A. Burns, R.I. Davis, "A survey of research into mixed criticality systems", ACM Computer Surveys, 50(6):1-37, 2017.

2. S.K. Baruah, S. Vestal, "Schedulability analysis of sporadic tasks with multiple criticality speciﬁcations," in 2008 Proceedings of the 20th Euromicro Conference on Real-Time Systems (ECRTS), Prague, Czech.

3. A. Agarwal, C. Iskander, R. Shankar, "Survey of Network on Chip (NoC) Architectures & Contributions," Journal of Engineering, Computing and Architecture, 3(1), 2009.

4. R. Kamal, N. Yadav, "NoC and Bus Architecture: a comparison", International Journal of Engineering Science and Technology (IJEST), 4(4), April 2012.

5. A. Achballah, S. Saoud "A Survey of Network-On-Chip Tools", International Journal of Advanced Computer Science and Applications (IJACSA), 4(9), 2013.

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