1. A Signed Binary Multiplication Technique;A D Booth;Quarterly J. Mechanical Applications in Math,1951
2. Parallel Architecture Modified Booth Multiplier;A R Cooper;Proceedings of the Institution of Electrical Engineers,1988
3. A Subnanosecond Josephson 16-bit ALU;S Kotani;IEEE Journal of Solid-State Circuits,1988
4. High-Speed Booth Encoded Parallel Multiplier Design;W C Yeh;IEEE Transactions on Computers,2000
5. VLSI Design of Low Power Booth Multiplier;N Bano;International Journal of Scientific & Engineering Research,2012