1. An ultra-low-jitter, mmW-band frequency synthesizer based on digital subsampling PLL using optimally spaced voltage comparators;J Kim;IEEE Journal of Solid-State Circuits,2019
2. A 28-nm FD-SOI 115-fs jitter PLLbased LO system for 24-30-ghz sliding-IF 5G transceivers;S Ek;IEEE Journal of Solid-State Circuits,1988
3. A -31dBc integrated-phase-noise 29 GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers;H Yoon;IEEE International Solid-State Circuits Conference -(ISSCC),2018
4. Optimal PAM order for wireline communication;A Wahid;2021 IEEE International Symposium on Circuits and Systems (ISCAS),2021
5. A 14-GHz bang-bang digital PLL with sub-150-fs integrated jitter for wireline applications in 7-nm FinFET CMOS;D Pfaff;IEEE Journal of Solid-State Circuits,2020