Detection of Stuck Open and Short Fault in SRAM Based System

Author:

Chitra A,Vijay Murugan S,Sathiyabhama B

Publisher

Elsevier BV

Reference24 articles.

1. A BIST pattern generator design for near-perfect fault coverage;M Chatterjee;IEEE Trans. Comput,2003

2. Bit-swapping LFSR and scan-chain ordering: A novel technique for peak-and average-power reduction in scanbased BIST;A S Abu-Issa;IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst,2009

3. An efficient scan tree design for compact test pattern set;S Banerjee;IEEE Trans. Comput.-Aided Des

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1. Study on Paradigm of Variable Length SRAM Embedded Memory Testing;2021 5th International Conference on Electronics, Communication and Aerospace Technology (ICECA);2021-12-02

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