1. Low power parallel multiplier design for DSP applications through coefficient optimization;Sangjin Hong;Proceedings. Twelfth Annual IEEE International,1999
2. Modest power savings for applications dominated by switching of large capacitive loads;Mark Hahm;Low Power Electronics,1994
3. Multiplier energy reduction through bypassing of partial products;Jun-Ni Ohban;Circuits and Systems, 2002. APCCAS'02. 2002 Asia-Pacific Conference on,2002