1. Future memory technology: challenges and opportunities;K Kim;Proceedings of International Symposium on VLSI Technology, Systems and Applications,2008
2. 90 nm Multi-level-cell flash memory technology;K Pangai;IEEE International Symposium on Semiconductor Manufacturing,2010
3. Strength-reduced parallel chien search architecture for strong BCH codes;J Cho;IEEE Transaction on Circuits and Systems,2008
4. A MPCN-based parallel architecture in BCH decoders for NAND flash memory devices;Y M Lin;IEEE Transaction on Circuits and Systems,2011