Author:
Wang Chua-Chin,Chodisetti L. S. S. Pavan Kumar,Kamarajugadda Durga Srikanth,Jose Oliver Lexter July Alvarez,Vellanki Pradyumna
Reference15 articles.
1. Low power high speed 1-bit full adder circuit design at 45nm CMOS technology;A K Yadav;Proc. 2017 Int. Conf. Recent Innovations Signal Process. Embedded Syst. (RISE),2017
2. Design of high-speed hybrid full adders using FinFET 18nm technology;A Raghunandan;Proc. 2019 4th Int. Conf. Recent Trends Electron,2019
3. Power consumption of static and dynamic CMOS circuits: a comparative study;E Macii;Proc. 2nd Int. Conf. ASIC, 1996
4. A 20 GHz 8-bit all-n-transistor logic cla using 16-nm FinFET technology;T.-J Lee;Proc. 2021 IEEE Asia Pacific Conf. Circuit Syst. (APCCAS),2021
5. A robust single phase clocking for low power, high-speed VLSI applications;M Afghahi;IEEE Journal of Solid-State Circuits,1996