Affiliation:
1. Faculty of Engineering, Universiti Malaysia Sarawak, 94300 Kota Samarahan, Sarawak, Malaysia
2. Graduate School of Information, production and Systems, Waseda University, 2-7 Hibikino, Wakamatsu-ku, Kitakyushu-shi, Fukuoka 808-0135, Japan
Abstract
Hash Function in cryptography algorithms is used to encrypt the message by giving the appropriate output based on the structure of the hash function itself. This algorithm is important for security applications such as Keyed-Hash Message Authentication Code (HMAC), digital signature, and others. There are different types of hash functions such as MD5, SHA-1, RIPEMD-160, SHA-256, SHA-224, SHA-384, SHA-512, and others. In this paper, the unfolding transformation method was proposed to improve the throughput of the SHA-256 hash function. Three types of SHA-256 hash function were designed namely SHA-256 design, SHA-256 design inner pipelining with unfolding factor 2, and SHA-256 design inner pipelining with unfolding factor 4. The designs were written in Verilog code and the output simulations were verified using ModelSim. The simulation results showed that the proposed SHA-256 inner pipelining unfolding with factor 4 provided the highest throughput which is 4196.30 Mbps, and factor 2 was superior in terms of maximum frequency and was better than the conventional SHA-256 design.
Type of Paper: other.
Keywords: Cryptography algorithm; FPGA; SHA-256 Hash Function; Unfolding transformation, Verilog
Publisher
Global Academy of Training and Research (GATR) Enterprise
Reference18 articles.
1. (NIST), N. I. (August 2015). Secure Hash Function. Federal Information Processing Standards (FIPS) Publication 180-4.
2. (1999). In K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation (pp. 119 - 140). John Wiley & Sons, Inc.
3. Kahri, F., Mestiri, H., Bouallegue, B. and Machhout, M., 2015, March. Efficient FPGA hardware implementation of secure hash function SHA-256/Blake-256. In 2015 IEEE 12th International MultiConference on Systems, Signals & Devices (SSD15) (pp. 1-5). IEEE. 10.1109/SSD.2015.7348105
4. IEEE 12th International Multi-Conference on Systems, Signals & Devices (SSD15), (pp. 1-5). H. Mestiri, F. K. (2015). Efficient FPGA Hardware Implementation of Secure Hash Function SHA-2. IJCNIS, Vol. 7(No. 1), 9-15.
5. Michail, H., Kakarountas, A., Milidonis, A. and Goutis, C., 2008. A top-down design methodology for ultrahigh-performance hashing cores. IEEE Transactions on Dependable and secure computing, 6(4), pp.255- 268. DOI: 10.1109/TDSC.2008.15