Digital Implementation of Neural Network by Partial Reconfiguration

Author:

Kumar C. Udhaya1,Saravanan P.2,Thiyagarajan N.3,Raj Veena4

Affiliation:

1. Bodhi Computing, India

2. PSG College of Technology, Coimbatore, India

3. Sri Eshwar College of Engineering, Coimbatore, India

4. Universiti Brunei Darussalam, Brunei

Abstract

Artificial Neural Networks (ANNs) are becoming increasingly important in the present technological era due to their ability to solve complex problems, adapt to new inputs, and improve decision-skills for different domains. The human brain serves as a model for Artificial Neural Networks (ANNs), a type of machine learning, as a reference for both structure and function. The existing work on ANNs supports tasks, such as regression, classification and pattern recognition separately. The discussion aims at resolving the above highlighted issues related to various ANN architectural implementations, considering the dynamic function exchange feature of FPGAs. With the aid of Zynq SOC, CNN and DNN architectures are designed in its Processing System, and the structure is accelerated using Programmable Logic. It also solves the issues due to trojans on design files, by introducing cryptography within the accelerator.

Publisher

IGI Global

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