An Enhanced Method for Running Embedded Applications in a Power-Efficient Manner

Author:

Kumar N. M. G.1,Ahmad Ayaz2,Gowda V. Dankan3ORCID,Lokesh S.4,Kadam Kirti Rahul Rahul5

Affiliation:

1. Sree Vidyanikethan Engineering College, Mohan Babu University, India

2. National Institute of Technology, Mahendru, India

3. B.M.S. Institute of Technology and Management, India

4. PSG Institute of Technology and Applied Research, India

5. Institute of Management Kolhapur, Bharati Vidyapeeth (Deemed), India

Abstract

Many modern items that are in widespread use have embedded systems. Due of embedded processing's ability to provide complex functions and a rich user experience, it has grown commonplace in many types of electronic products during the last 20 years. Power consumption in embedded systems is regarded as a crucial design criterion among other factors like area, testability, and safety. Low power consumption has therefore become a crucial consideration in the design of embedded microprocessors. The proposed new method takes into consideration both the spatial and temporal locality of the accessed data. In the chapter, the new cache replacement is combined with an efficient cache partitioning method to improve the cache hit rate. In this work, a new modification is proposed for the instruction set design to be used in custom made processors.

Publisher

IGI Global

Reference30 articles.

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3. Chen, G., Hu, B., Huang, K., Knoll, A., & Huang, K. (2019). Automatic cache partitioning and timetriggered scheduling for real-time MPSoCs. International Conference on ReConFigurable Computing and FPGAs (ReConFig14), 1-8.

4. Chen, G., Huang, K., Huang, J., & Knoll, A. (2019). Cache Partitioning and Scheduling for Energy Optimisation of Real-Time MPSoCs. IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, 35-41.

5. Design, implementation, and performance evaluation of a detection-based adaptive block replacement scheme

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