Power-Efficient Stochastic Number Generator Design and Implementation for Encryption

Abstract

Stochastic computing utilizes random bit streams to encode continuous data efficiently. One important aspect is the stochastic number generator (SNG) that encodes numbers into random binary bit streams. This work presents power-efficient 4-bit and 8-bit SNGs by using a modified Non-linear Feedback Shift Register (NLFSR) as the random number source and a Weighted Binary Generator (WBG) as the probability conversion circuit. A bipartite approach is employed to reduce power and delay consumption in the SNGs. Additionally, the concept of sharing a single random number source with multiple probability conversion circuits is explored to achieve further power savings. This project offers enhanced power efficiency in SNGs, contributing to advancements in stochastic computing and power circuit designs. The main application of this project is encryption, as random number sequences are required for various stages of encryption protocols.