Silicon Validation of GALS Methods and Architectures in a State-of-the-Art CMOS Process

Abstract

The GALS methodology has been discussed for many years, but only a few relevant implementations in silicon have been done. This chapter describes the implementation and test of the Moonrake Chip – a complex GALS demonstrator implemented in 40 nm CMOS technology. Two novel types of GALS interface circuits are validated: point-to-point pausible clocking GALS interfaces and GALS NoC interconnects. Point-to-point GALS interfaces are integrated within a complex OFDM baseband transmitter block, and for NoC switches special test structures are defined. This chapter discloses the full structure of the respective interfaces, the complete GALS system, as well as the design flow utilized to implement them on the chip. Moreover, the full set of measurement results are presented, including area, power, and EMI results. Significant benefits and robustness of our applied GALS methodology are shown. Finally, some outlook and vision of the future role of GALS are outlined.