Low Complexity Processor Designs for Energy-Efficient Security and Error Correction in Wireless Sensor Networks

Abstract

This chapter presents low complexity processor designs for energy-efficient security and error correction for implementation on wireless sensor networks (WSN). WSN nodes have limited resources in terms of hardware, memory, and battery life span. Small area hardware designs for encryption and error-correction modules are the most preferred approach to meet the stringent design area requirement. This chapter describes Minimal Instruction Set Computer (MISC) processor designs with a compact architecture and simple hardware components. The MISC is able to make use of a small area of the FPGA and provides a processor platform for security and error correction operations. In this chapter, two example applications, which are the Advance Encryption Standard (AES) and Reed Solomon (RS) algorithms, were implemented onto MISC. The MISC hardware architecture for AES and RS were designed and verified using the Handel-C hardware description language and implemented on a Xilinx Spartan-3 FPGA.