S-? Fractional-N Phase-Locked Loop Design Using HDL and Transistor-Level Models for Wireless Communications

Abstract

This chapter presents a systematic design of a S-? fractional-N Phase-Locked Loop based on hardware description language behavioral modeling. The proposed design consists of describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The description language models of critical PLL blocks have been described in VHDL-AMS, which is an IEEE standard, to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the overall system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models in the frequency range around 2.45 GHz for wireless applications.