Low Complexity Minimal Instruction Set Computer Design using Anubis Cipher for Wireless Identification and Sensing Platform

Abstract

This chapter presents a low complexity processor design for efficient and compact hardware implementation for WISP system security using the involution cipher Anubis algorithm. WISP has scarce resources in terms of hardware and memory, and it is reported that it has 32K of program and 8K of data storage, thus providing sufficient memory for design implementation. The chapter describes Minimal Instruction Set Computer (MISC) processor designs with a flexible architecture and simple hardware components for WISPs. The MISC is able to make use of a small area of the FPGA and provides security programs and features for WISPs. In this chapter, an example application, which is Anubis involution cipher algorithm, is used and proposed to be implemented onto MISC. The proposed MISC hardware architecture for Anubis can be designed and verified using the Handel-C hardware description language and implemented on a Xilinx Spartan-3 FPGA.