Multiplier for DSP Application in CPS System

Abstract

A cyber-physical system over field-programmable gate array with optimized artificial intelligence algorithm is beneficial for society. Multiply and accumulate (MAC) unit is an integral part of a DSP processor. This chapter is focused on improving its performance parameters MAC based on column bypass multiplier. It highlights DSP's design for intelligent applications and the architectural setup of the broadly useful neuro-PC, based on the economically available DSP artificial intelligence engine (AI-engine). Adaptive hold logic in the multipliers section determines whether another clock cycle is required to finish multiplication. Adjustment in algorithm reduced the aging impact over cell result in the processor last longer and has increased its life cycle.