Affiliation:
1. Vel Tech Rangarajan Dr. Sagunthala R and D Institute of Science and Technology, India
2. Anna University, India
3. National Institute of Technology, Delhi, India
Abstract
In this chapter, an efficient FPGA architecture is proposed to categorize and analyze the sleep level. This proposed architecture is implemented using four sub parts which are namely preprocessing unit, FIR filtering, self-regulated learning, and fuzzy deduction. The EEG (electro encephalo gram) and EMG (electro myogram) are signal samples are considered for the analysis of this sleep level. The signals are initially preprocessed to remove undesired signal components. Further, a reconfigurable multichannel multiply accumulate (MAC)-based FIR filter is utilized for achieving the desired signal. Then the signal is classified based on the reference data with the use of self-regulated machine learning and fuzzy deduction schemes which involves averaging and thresholding process. Further, the signals are categorized into completely awake level, partially awake level, and sleep level using fuzzy if-then rules. The performance parameters are analyzed in terms of sensitivity, specificity, latency, area occupied, power consumption, and speed enhancement.