1. High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core
2. Architecture of the Pentium microprocessor
3. Arahata, F., Nishii, O., Uchiyama, K., & Nakagawa, N. (February, 1997). Functional verification of the superscalar SH-4 microprocessor, In Compcon97, the Proceedings of the International conference, Compcon97, (pp. 115-120).
4. Canedo, A. (September, 2006). Code Generation Algorithms for Consumed and Produced Order Queue Machines. Master’s thesis, University of Electro-Communications, Tokyo, Japan.
5. Canedo, A., Abderazek, B. A., & Sowa, M. (May, 2006). A GCC-based Compiler for the Queue Register Processor (QRP-GCC), In IWMST2006, The 2006 International Workshop on Modern Science and Technology, Wuhan, (pp. 250-255).