A High-Throughput Architecture for the SHA-256/224 Compliant With the DSRC Standard-Reference-Cited by-同舟云学术

A High-Throughput Architecture for the SHA-256/224 Compliant With the DSRC Standard

Published:2019-01 Issue:1 Volume:10 Page:98-118
ISSN:1947-3176
Container-title:International Journal of Embedded and Real-Time Communication Systems
language:en
Short-container-title:

Author:

Ben Dhaou Imed Saad¹,Tenhunen Hannu²

Affiliation:

1. Qassim University, Buraidah, Saudi Arabia & University of Monastir, Tunisia

2. Royal Institute of Technology, Kista, Sweden

Abstract

This article presents a word serial retimed architecture for the SHA-256/224 algorithm. The architecture is compliant with the dedicated-short range communication for safety message authentications. We elaborate three-operand adder architectures suitable for field programmable gate array implementation. Several transformation techniques at the data-flow-graph level have been used to derive the architecture. Synthesis results show that the architecture has high throughput/ slice value compared with state-of-the-art SHA-256 implementations. The article also promulgates a comparison between high-level synthesis and RTL design.

Publisher

IGI Global

Subject

General Computer Science

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