Fault Coexistence and Grading Aware TSV Test based on Delay Feature

Abstract

Screening out the defects in the TSV manufacturing process and eliminating the resistive open fault and leakage fault as early as possible are beneficial to improve the yield and reliability of 3D ICs. The existing prebond test methods are confined to the test accuracy and de- tection range, especially the test confusion prob- lem and the lack of diagnosable ability under the coexistence of multiple faults. Based on the uc- tuation of delay feature caused by faults, a kind of fault coexistence and grading aware TSV test method is proposed to enhance the yield and reli- ability of TSVs in this paper. The reference TSV and the TSV under test are input with test stim- uli simultaneously. Furthermore, the designed delay extraction circuit is utilized to generate the rising edge and the falling edge separately and additional fault grading circuit can be enriched according to the test requirements. Finally, a one bit comparator at the capture end is used to detect whether two pulse signals arrive simul- taneously, so as to determine whether there is a fault and the type of fault. The simulation results indicate that the detection range of resistive open fault is more than 281 , and the detection range of leakage fault is less than 223 M , which is bet- ter than most existing methods. While effective- ly solving resistive open fault and leakage fault, it can also successfully deal with the coexistence of two kinds of faults and achieve a 5-level fault grading ability with relatively low area overhead.