Design of High-speed Delay-FXLMS Hardware Architecture Based on FPGA

Abstract

In order to improve the convergence and clock speed of DFxLMS adaptive filter, a hardware architecture of fine-grained retiming DFxLMS (HS-TF-RDFXLMS) filter in the form of hardware sharing transpose is proposed. Firstly, the architecture adopts delay decomposition algorithm to solve the problem that the convergence of filter decreases due to the increase of delay and output lag. Secondly, on the premise that the algorithm performance remains unchanged, the adaptive filter module and the secondary path module are transposed to further reduce the critical path to improve the clock speed of the system. The number of registers is reduced by optimizing circuit sub-module. Finally, the area/speed tradeoff of TF-RDFXLMS filter is realized by hardware sharing on the basis of constant critical path. Experimental results show that the convergence speed of the algorithm is 3.5 times that of DFxLMS algorithm, and the critical path is shortened by ([log2N]+1)TADD. The circuit structure of adaptive filter designed in this paper is realized by Xilinx Artix7 FPGA platform. The clock speed of HS-TF-RDFXLMS filter is reduced by 4.386% compared with TF-RDFXLMS filter. However, the resources of LUT and FF are saved by 10.964% and 28.322% respectively. The power consumption is 150.73 mW. This improves the performance of the system.