Design and Performance Analysis of Low Power and High Throughput of Analog Data Compression and Decompression using ANN in 32nm FinFET Technology

Abstract

The development and fabrication of integrated circuits for the applicational areas of VLSI such as processing of the signal, medicine tomography, telecommunication turn out to be a novel technology for the upcoming innovations. The fabrication of IC’s is attributable to the methodology in the technology of VLSI and when compared to artificial Neural Network, the genetic performance of these productions is approximately the same and are typically employed for diagnosing the syndrome, compression as well as the decompression of signal used in the medical domain. Techniques such as HMM, DCT, as well as PCA are employed for compression and decompression of signals but these approaches still possess some disadvantages. Therefore, to overcome these issues, a chip-level design for Artificial Neural Network is proposed that makes use of FinFET 32 nm technology and includes sigmoid activation function (SAF), Gilbert cell number, as well as bias circuits to prolong the compressed magnitude relation and accuracy. As a result, with the help of the Cadence Virtuoso analog tool, the Artificial Neural Network has been designed using FinFET 32nm technology along with all the details of sub-units such as Layout vs Schematic (LVS), Design rule check (DRC), RC extraction as well as chip level (GDS-II). Feed Forward Artificial Neural Network (FWANN) is considered as one of the most basic types of ANN and it is implemented using the concept of Back Propagation (BP). The simulation results of the suggested 16-bit 6TRAM cell were found to have 8%, 21%, and 0.9% improvement in consuming power, delay, and compressed data losses respectively.