The low threshold-voltage shift with temperature and small subthreshold-slope in 28 nm UTBB FDSOI for 300 °C high-temperature application

Abstract

Abstract Partially depleted silicon-on-insulator (PDSOI) MOSFETs are widely used in 225 °C high-temperature electronic system applications with integrated circuits. But the process node stays at 0.5 µm for a long time and no further breakthrough can be achieved. This paper reports the high-temperature characteristics of 28 nm ultra-thin body and box fully depleted SOI (FDSOI) CMOS transistors with low threshold voltage (LVT) structure. Experimental results demonstrate that V t shift changes with temperature as low as 0.59 mV °C−1, the subthreshold slope (SS) is 145.35 mV dec−1 at 300 °C, and the related parameters are optimized by 3.7 times and 2.2 times respectively compared with 0.13 µm PDSOI. Combined with theoretical analysis, it is proved that the ultra-body FDSOI has an LVT drift rate and better SS than 0.13 µm PDSOI at high temperature. The advantage of this performance is mainly due to the difference between α VT α VT and β VT coefficients related to the back gate effect. Under negative back-gate bias, the I on/l off ratio can be increased by two orders of magnitude without affecting V t shift changes with temperature, this proves that the FDSOI is capable of high-temperature applications above 300 °C. This paper provides substantial support for future high-temperature system integrated circuits from the micro-scale to the nano-scale.