Superior resistance switching in monolayer MoS2 channel-based gated binary resistive random-access memory via gate-bias dependence and a unique forming process

Abstract

Abstract Resistance switching (RS) in 2D molybdenum disulfide (MoS2) was recently discovered. Since the discovery, many reports demonstrating MoS2 resistive random-access memory (RRAM) with synapse-like behavior have been published. These reports strongly justify applications of MoS2 RRAM in neuromorphic hardware as well as an alternative to conventional binary memories. In this work, we unveil the effect of RS, induced by current–voltage hysteresis cycles across CVD-grown monolayer MoS2-based gated RRAM, on its transistor’s electrical and reliability characteristics. A unique gate voltage dependence on the RS is identified which has a remarkable impact on the switching performance of MoS2 RRAM. RS behavior was found to be significantly dependent on the charge conduction in the channel. Moreover, we have shown a potential device-forming event when MoS2-gated RRAMs were subjected to a steady-state electrical stress. Both hysteresis and steady-state electrical stress were found to disturb the transistor action of these gated RRAMs, which can in fact be used as a signature of RS. Interestingly, current–voltage hysteresis resulted in unipolar RS, whereas steady-state electrical stress before RS measurement led to bipolar RS. Moreover, successive stress cycles of such electrical stress lead to multiple resistance states, a behavior similar to synaptic properties such as long-term potentiation and long-term depression, typically found in memristors. We find that the charge transport mechanism dominant in the MoS2 FET, in conjunction with steady-state stress-induced device forming, determine the extent of RS induced in thes MoS2-based gated RRAMs. Finally, on the basis of insights developed from the dependence on the charge transport mechanism and steady-state stress-induced forming of the MoS2 channel, we propose a certain steady-state electrical stress condition which can be used as a ‘forming’ process, employed prior to the use of MoS2-based binary RRAMs for improved switching performance.