Development of SRAM-APB protocol interface and verification

Abstract

Abstract The purpose of this mechanism is to enhance the chip’s internal connections and read/write memory capabilities. The Advanced Microcontroller Bus Architecture (AMBA) is one such shared bus that uses static random-access memory to achieve this goal. As a result, it’s important to weigh a variety of design options before diving into the Verilog description. It’s also important to remember that the system must be designed to accommodate a large number of interoperable modules and memories. The design, on the other hand, starts with fewer modules and a less complicated description and realisation that relies on memory access. ModelSim is used to simulate after the delay has been modelled in Verilog. Since the interface’s static random-access memory uses an APB protocol, its performance may be tested at this stage. In addition, Questasim employs verification modules and System Verilog technologies to guarantee the system’s operation. From the obtained results, the Direct Memory Access (DMA) with SRAM-APB outperforms the alternatives, particularly in frame transmission schemes, with a wire efficiency that is 1.4 times higher and a dynamic energy efficiency that is nearly twice as high as those of conventional configurations.