Gate‐all‐around nanowire vertical tunneling FETs by ferroelectric internal voltage amplification

Abstract

Abstract This work illustrates the most effective way of utilizing the ferroelectricity for tunneling field-effect transistors (TFETs). The ferroelectric (Hf0.5Zr0.5O2) in shunt with gate-dielectric is utilized as an optimized metal–ferroelectric–semiconductor (OMFS) option to improve the internal voltage (V int ) for ample utilization of polarization and electric fields of Hf0.5Zr0.5O2 across the tunneling region. The modeling of V int signifies 0.15–1.2 nm reduction in tunneling length (λ) than the nominal metal–ferroelectric–insulator–semiconductor (MFIS) option. Furthermore, the TFET geometry with the scaled-epitaxy region as vertical TFET (VTFET), strained Si0.6Ge0.4 as source, and gate-all-around nanowire options are used as an added advantage for further enhancement of TFET’s performance. As a result, the proposed design (OMFS-VTFET) achieves superior DC and RF performances than the MFIS option of TFET. The figure of merits in terms of DC characteristics in the proposed and optimized structure are of improved on-current (=0.23 mA μm−1), high on-to-off current ratio (=1011), steep subthreshold swing (=33.36 mV dec−1), and superior unity gain cut-off frequency (≥300 GHz). The design is revealed as energy-efficient with significant reduction of energy-efficiency in both logic and memory applications.