Bilateral sidewall engineering Si1–x Ge x iTFET for low power display application *

Abstract

Abstract In this work, we demonstrate the performance enhancement of bottom-gated inductive line-tunneling TFET (iTFET) through the integration of bilateral sidewall engineering with SiGe mole fraction variation, considering the feasibility of the fabrication process. We also employ a metal-semiconductor interface for carrier induction to improve the I ON, resulting in a lower subthreshold swing average (S.S avg). Using Sentaurus TCAD simulations, we show that the dominant current mechanism is line tunneling, and the hump effect is mitigated by using SiGe with different mole fractions on the sidewalls. Compared to conventional tunnel field-effect transistors, which require at least three doping processes and annealing, the proposed device requires only one doping process and utilizes the metal-semiconductor interface for carrier induction, significantly reducing the fabrication cost and thermal budget. These measurement based simulations show that the S.S avg is improved to 21.5 mV dec−1 with an I ON/I OFF ratio of 106 at V D = 0.2 V. This is the first time that a TFT with a subthreshold swing of less than 60 mV dec−1 has been proposed, so it will save much more power in the future and displays with high energy efficiency can be realized and widely used in IoT applications.