Impact of interfacial layer thickness on gate stack-based DGTFET: an analog/RF prospective

Abstract

Abstract In this work, influence of interfacial layer thickness on gate-stack based double gate (DG) TFET device concerning analog/RF performance has been studied. Through simulation, it has been found that thicker interfacial layer can be used to mitigate the deprivation inRF/analog performance instigated with high -K gate dielectric. In this article, we have varied the thickness (Ti) of interfacial layer ranging from 0.2 nm to0.7nm and analyzed its effect. The decline in the intrinsic dc gain (δAV = Av(K = 3.9) - Av (K = 40)), maximum oscillation frequency (δfMAX = fMAX(K = 3.9) - fmax(K = 40)) and the cut -off frequency (AfT = fT(K = 39) - fT(K = 40)) is 27.1 dB, 8 GHz and 6.4 GHz, respectively for TI = 0.2nm and24 dB, 1.7 GHz,&3.5 GHz, respectively in case ofTI = 0.7nm which indicates that if interfacial layer is thick (0.7nm), then, it is advantageous as compared to thickness of 0.2nm. Thus, such a device design not only decreases the surface lattice mismatching effect, but also, is more promising for better analog/RF performance of TFET device.