Modelling and Failure Analysis of SiC MOSFET under the Effects of Parasitic Parameters

Abstract

Abstract Recent years, SiC MOSFET has been gradually utilized in high power devices. However, it has become one of the highest failure rate devices in circuit systems. Its failure relates to the degradation which caused by the hot carrier injection(HCI) effect. Because the parasitic parameters make the oscillations in switching processes more intense, the switching time and voltage overshoot increases, and thus HCI effect exacerbates. So, it is necessary to analyse the influence of parasitic parameters on the failure of SiC MOSFET. In this paper, an improved SiC MOSFET model with all key parasitic parameters is built to set up an accurate test circuit. The parasitic parameters were divided into four parts: body diode, parasitic resistance, parasitic capacitance and parasitic inductance. According to the simulation, it concluded that only the parasitic inductance has a great impact on the HCI effect and the impacts are different according to the different locations of parasitic inductance. The influence of the parasitic inductance on the load circuit and near the source is much greater than other parts. Their increase greatly increases switching time and voltage overshoot, and thus exacerbates HCI effect and accelerates the degradation of SiC MOSFET.