Abstract
Abstract
Due to the COVID-19 pandemic, distance education starts playing a crucial role in higher education and the need for development of educational tools, helping the students learn better at home cannot be ignored. Teaching programming languages online is a complicated task and when the course subject is programmable logic design through Hardware Description Languages (HDLs), online teaching becomes a complex challenge. In this paper is presented a concept of a training environment that uses the visual programing technique to help the students create VHDL models of various digital devices. The students construct VHDL models by combining simple visual objects while the environment is providing guidance in real time and is preventing a wrong match of VHDL operators and signals. The strategy for building a model of a compex digital circuit by moving and connecting visual objects will help the students with visual kinaesthetic learning style to internalize the concept and the structure of the VHDL model. The training environment will benefit mostly the students, learning in distance mode, but it is also useful for face-to-face students, who find it difficult to assimilate the specifics of VHDL modelling.