Analysis of effectiveness of power on refined numerical models of floating point arithmetic unit for biomedical applications

Abstract

Abstract “The technology defined today might be redefined tomorrow”- from the quotes, in the modern era redefining the architecture with the optimization of area, delay and reduction of power is focused more than fixed models. This paper describes the floating point arithmetic unit and insists the importance of it, in real time signal processing. The present trends of portable devices for medical applications need occupancy of smaller area with long span time life of battery. The bio medical signals are converted into IEEE 754 format as BIF. Hence it is easily analyzed in FPGAR devices and also this work insists the importance of redefining the architecture with reduction of critical path delay. The FPU arithmetic unit has the blocks to perform the computations like addition, Multiplication and division operation. The main architecture is constructed using top level design with individual blocks defined as a part of it. The floating point unit defined with modern FPGAR (Reconfigurable FPGA) increase the speed of computation and enables the flexibility and adopted to the hardware reconfigurable models. A 32 bit representation of IEEE 754 results of FPU is stored in the data storage and this process optimize the critical path between blocks. The way its programmed consumes lower level of power consumption in the range of 50.4 nw and delay of 25.2 ns and also modern adder structure with 6T type was used to implement the intermediate blocks of multiplier in FPU block as part of computing partial products. By this process of FPU redefining, reduce the number of slice to 206 and increase the operating frequency of 46.12 MHz.